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PM3-Cable-Monitor
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Core Register type definitions. More...
Topics | |
| Nested Vectored Interrupt Controller (NVIC) | |
| Type definitions for the NVIC Registers. | |
Classes | |
| union | APSR_Type |
| Union type to access the Application Program Status Register (APSR). More... | |
| union | IPSR_Type |
| Union type to access the Interrupt Program Status Register (IPSR). More... | |
| union | xPSR_Type |
| Union type to access the Special-Purpose Program Status Registers (xPSR). More... | |
| union | CONTROL_Type |
| Union type to access the Control Registers (CONTROL). More... | |
Core Register type definitions.
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _FLD2VAL | ( | field, | |
| value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Mask and shift a register value to extract a bit filed value.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of register. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define _VAL2FLD | ( | field, | |
| value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Mask and shift a bit field value for use in a register bit range.
| [in] | field | Name of the register bit field. |
| [in] | value | Value of the bit field. This parameter is interpreted as an uint32_t type. |
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
APSR: C Mask
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_C_Pos 29U |
APSR: C Position
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
| #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) |
APSR: GE Mask
| #define APSR_GE_Pos 16U |
APSR: GE Position
| #define APSR_GE_Pos 16U |
APSR: GE Position
| #define APSR_GE_Pos 16U |
APSR: GE Position
| #define APSR_GE_Pos 16U |
APSR: GE Position
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
APSR: N Mask
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_N_Pos 31U |
APSR: N Position
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
APSR: Q Mask
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_Q_Pos 27U |
APSR: Q Position
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
APSR: V Mask
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_V_Pos 28U |
APSR: V Position
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
APSR: Z Mask
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define APSR_Z_Pos 30U |
APSR: Z Position
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
| #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) |
CONTROL: FPCA Mask
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
| #define CONTROL_FPCA_Pos 2U |
CONTROL: FPCA Position
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
CONTROL: nPRIV Mask
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_nPRIV_Pos 0U |
CONTROL: nPRIV Position
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
| #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) |
CONTROL: SFPA Mask
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
| #define CONTROL_SFPA_Pos 3U |
CONTROL: SFPA Position
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
CONTROL: SPSEL Mask
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CONTROL_SPSEL_Pos 1U |
CONTROL: SPSEL Position
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
| #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) |
Core Debug configuration struct
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_BASE (0xE000EDF0UL) |
Core Debug Base Address
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
CoreDebug DAUTHCTRL: INTSPIDEN Mask
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
CoreDebug DAUTHCTRL: INTSPIDEN Position
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
CoreDebug DAUTHCTRL: SPIDENSEL Mask
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
CoreDebug DAUTHCTRL: SPIDENSEL Position
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
CoreDebug DAUTHCTRL: SPNIDENSEL Position
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
CoreDebug DCRSR: REGSEL Mask
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
CoreDebug DCRSR: REGSEL Position
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
CoreDebug DCRSR: REGWnR Mask
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
CoreDebug DCRSR: REGWnR Position
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
CoreDebug DEMCR: MON_EN Mask
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
CoreDebug DEMCR: MON_EN Position
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
CoreDebug DEMCR: MON_PEND Mask
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
CoreDebug DEMCR: MON_PEND Position
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
CoreDebug DEMCR: MON_REQ Mask
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
CoreDebug DEMCR: MON_REQ Position
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
CoreDebug DEMCR: MON_STEP Mask
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
CoreDebug DEMCR: MON_STEP Position
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
CoreDebug DEMCR: TRCENA Mask
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
CoreDebug DEMCR: TRCENA Position
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
CoreDebug DEMCR: VC_BUSERR Mask
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
CoreDebug DEMCR: VC_BUSERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
CoreDebug DEMCR: VC_CHKERR Mask
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
CoreDebug DEMCR: VC_CHKERR Position
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
CoreDebug DEMCR: VC_CORERESET Mask
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
CoreDebug DEMCR: VC_CORERESET Position
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
CoreDebug DEMCR: VC_HARDERR Mask
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
CoreDebug DEMCR: VC_HARDERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
CoreDebug DEMCR: VC_INTERR Mask
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
CoreDebug DEMCR: VC_INTERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
CoreDebug DEMCR: VC_MMERR Mask
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
CoreDebug DEMCR: VC_MMERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
CoreDebug DEMCR: VC_NOCPERR Mask
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
CoreDebug DEMCR: VC_NOCPERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
CoreDebug DEMCR: VC_STATERR Mask
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
CoreDebug DEMCR: VC_STATERR Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
CoreDebug DHCSR: C_DEBUGEN Mask
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
CoreDebug DHCSR: C_DEBUGEN Position
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
CoreDebug DHCSR: C_HALT Mask
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
CoreDebug DHCSR: C_HALT Position
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
CoreDebug DHCSR: C_MASKINTS Mask
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
CoreDebug DHCSR: C_MASKINTS Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
CoreDebug DHCSR: C_SNAPSTALL Mask
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
CoreDebug DHCSR: C_SNAPSTALL Position
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
CoreDebug DHCSR: C_STEP Mask
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
CoreDebug DHCSR: C_STEP Position
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
CoreDebug DHCSR: DBGKEY Mask
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
CoreDebug DHCSR: DBGKEY Position
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
CoreDebug DHCSR: S_HALT Mask
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
CoreDebug DHCSR: S_HALT Position
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
CoreDebug DHCSR: S_LOCKUP Mask
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
CoreDebug DHCSR: S_LOCKUP Position
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
CoreDebug DHCSR: S_REGRDY Mask
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
CoreDebug DHCSR: S_REGRDY Position
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
CoreDebug DHCSR: S_RESET_ST Mask
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
CoreDebug DHCSR: S_RESET_ST Position
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
CoreDebug DHCSR: S_RESTART_ST Mask
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
CoreDebug DHCSR: S_RESTART_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
CoreDebug DHCSR: S_RETIRE_ST Mask
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
CoreDebug DHCSR: S_RETIRE_ST Position
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
CoreDebug DHCSR: S_SLEEP Mask
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
CoreDebug DHCSR: S_SLEEP Position
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
CoreDebug DSCSR: CDS Mask
| #define CoreDebug_DSCSR_CDS_Pos 16U |
CoreDebug DSCSR: CDS Position
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
CoreDebug DSCSR: SBRSEL Mask
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
CoreDebug DSCSR: SBRSEL Position
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
CoreDebug DSCSR: SBRSELEN Mask
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
CoreDebug DSCSR: SBRSELEN Position
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_BASE (0xE0001000UL) |
DWT Base Address
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) |
DWT CPICNT: CPICNT Mask
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CPICNT_CPICNT_Pos 0U |
DWT CPICNT: CPICNT Position
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) |
DWT CTRL: CPIEVTENA Mask
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CPIEVTENA_Pos 17U |
DWT CTRL: CPIEVTENA Position
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) |
DWT CTRL: CYCCNTENA Mask
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCCNTENA_Pos 0U |
DWT CTRL: CYCCNTENA Position
| #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) |
DWT CTRL: CYCDISS Mask
| #define DWT_CTRL_CYCDISS_Pos 23U |
DWT CTRL: CYCDISS Position
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) |
DWT CTRL: CYCEVTENA Mask
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCEVTENA_Pos 22U |
DWT CTRL: CYCEVTENA Position
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) |
DWT CTRL: CYCTAP Mask
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_CYCTAP_Pos 9U |
DWT CTRL: CYCTAP Position
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) |
DWT CTRL: EXCEVTENA Mask
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCEVTENA_Pos 18U |
DWT CTRL: EXCEVTENA Position
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) |
DWT CTRL: EXCTRCENA Mask
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_EXCTRCENA_Pos 16U |
DWT CTRL: EXCTRCENA Position
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) |
DWT CTRL: FOLDEVTENA Mask
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_FOLDEVTENA_Pos 21U |
DWT CTRL: FOLDEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) |
DWT CTRL: LSUEVTENA Mask
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_LSUEVTENA_Pos 20U |
DWT CTRL: LSUEVTENA Position
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) |
DWT CTRL: NOCYCCNT Mask
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOCYCCNT_Pos 25U |
DWT CTRL: NOCYCCNT Position
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) |
DWT CTRL: NOEXTTRIG Mask
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOEXTTRIG_Pos 26U |
DWT CTRL: NOEXTTRIG Position
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) |
DWT CTRL: NOPRFCNT Mask
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOPRFCNT_Pos 24U |
DWT CTRL: NOPRFCNT Position
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) |
DWT CTRL: NOTRCPKT Mask
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NOTRCPKT_Pos 27U |
DWT CTRL: NOTRCPKT Position
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) |
DWT CTRL: NUMCOMP Mask
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_NUMCOMP_Pos 28U |
DWT CTRL: NUMCOMP Position
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) |
DWT CTRL: PCSAMPLENA Mask
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_PCSAMPLENA_Pos 12U |
DWT CTRL: PCSAMPLENA Position
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) |
DWT CTRL: POSTINIT Mask
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTINIT_Pos 5U |
DWT CTRL: POSTINIT Position
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) |
DWT CTRL: POSTPRESET Mask
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_POSTPRESET_Pos 1U |
DWT CTRL: POSTPRESET Position
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) |
DWT CTRL: SLEEPEVTENA Mask
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SLEEPEVTENA_Pos 19U |
DWT CTRL: SLEEPEVTENA Position
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) |
DWT CTRL: SYNCTAP Mask
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_CTRL_SYNCTAP_Pos 10U |
DWT CTRL: SYNCTAP Position
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) |
DWT EXCCNT: EXCCNT Mask
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_EXCCNT_EXCCNT_Pos 0U |
DWT EXCCNT: EXCCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) |
DWT FOLDCNT: FOLDCNT Mask
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FOLDCNT_FOLDCNT_Pos 0U |
DWT FOLDCNT: FOLDCNT Position
| #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) |
DWT FUNCTION: ACTION Mask
| #define DWT_FUNCTION_ACTION_Pos 4U |
DWT FUNCTION: ACTION Position
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
| #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) |
DWT FUNCTION: CYCMATCH Mask
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
| #define DWT_FUNCTION_CYCMATCH_Pos 7U |
DWT FUNCTION: CYCMATCH Position
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
| #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) |
DWT FUNCTION: DATAVADDR0 Mask
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
| #define DWT_FUNCTION_DATAVADDR0_Pos 12U |
DWT FUNCTION: DATAVADDR0 Position
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
| #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) |
DWT FUNCTION: DATAVADDR1 Mask
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
| #define DWT_FUNCTION_DATAVADDR1_Pos 16U |
DWT FUNCTION: DATAVADDR1 Position
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
| #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) |
DWT FUNCTION: DATAVMATCH Mask
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
| #define DWT_FUNCTION_DATAVMATCH_Pos 8U |
DWT FUNCTION: DATAVMATCH Position
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) |
DWT FUNCTION: DATAVSIZE Mask
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_DATAVSIZE_Pos 10U |
DWT FUNCTION: DATAVSIZE Position
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
| #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) |
DWT FUNCTION: EMITRANGE Mask
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
| #define DWT_FUNCTION_EMITRANGE_Pos 5U |
DWT FUNCTION: EMITRANGE Position
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
| #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) |
DWT FUNCTION: FUNCTION Mask
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
| #define DWT_FUNCTION_FUNCTION_Pos 0U |
DWT FUNCTION: FUNCTION Position
| #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) |
DWT FUNCTION: ID Mask
| #define DWT_FUNCTION_ID_Pos 27U |
DWT FUNCTION: ID Position
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
| #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) |
DWT FUNCTION: LNK1ENA Mask
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
| #define DWT_FUNCTION_LNK1ENA_Pos 9U |
DWT FUNCTION: LNK1ENA Position
| #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) |
DWT FUNCTION: MATCH Mask
| #define DWT_FUNCTION_MATCH_Pos 0U |
DWT FUNCTION: MATCH Position
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) |
DWT FUNCTION: MATCHED Mask
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_FUNCTION_MATCHED_Pos 24U |
DWT FUNCTION: MATCHED Position
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) |
DWT LSUCNT: LSUCNT Mask
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_LSUCNT_LSUCNT_Pos 0U |
DWT LSUCNT: LSUCNT Position
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
| #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) |
DWT MASK: MASK Mask
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
| #define DWT_MASK_MASK_Pos 0U |
DWT MASK: MASK Position
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) |
DWT SLEEPCNT: SLEEPCNT Mask
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U |
DWT SLEEPCNT: SLEEPCNT Position
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
| #define FPU_BASE (SCS_BASE + 0x0F30UL) |
Floating Point Unit
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
| #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) |
FPCAR: ADDRESS bit Mask
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
| #define FPU_FPCAR_ADDRESS_Pos 3U |
FPCAR: ADDRESS bit Position
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
| #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) |
FPCCR: ASPEN bit Mask
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
| #define FPU_FPCCR_ASPEN_Pos 31U |
FPCCR: ASPEN bit Position
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
| #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) |
FPCCR: BFRDY bit Mask
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
| #define FPU_FPCCR_BFRDY_Pos 6U |
FPCCR: BFRDY Position
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
| #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) |
FPCCR: CLRONRET bit Mask
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
| #define FPU_FPCCR_CLRONRET_Pos 28U |
FPCCR: CLRONRET Position
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
| #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) |
FPCCR: CLRONRETS bit Mask
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
| #define FPU_FPCCR_CLRONRETS_Pos 27U |
FPCCR: CLRONRETS Position
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
| #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) |
FPCCR: HFRDY bit Mask
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
| #define FPU_FPCCR_HFRDY_Pos 4U |
FPCCR: HFRDY Position
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
| #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) |
FPCCR: Lazy state preservation active bit Mask
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
| #define FPU_FPCCR_LSPACT_Pos 0U |
FPCCR: Lazy state preservation active bit Position
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
| #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) |
FPCCR: LSPEN bit Mask
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
| #define FPU_FPCCR_LSPEN_Pos 30U |
FPCCR: LSPEN Position
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
| #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) |
FPCCR: LSPENS bit Mask
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
| #define FPU_FPCCR_LSPENS_Pos 29U |
FPCCR: LSPENS Position
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
| #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) |
FPCCR: MMRDY bit Mask
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
| #define FPU_FPCCR_MMRDY_Pos 5U |
FPCCR: MMRDY Position
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
| #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) |
FPCCR: MONRDY bit Mask
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
| #define FPU_FPCCR_MONRDY_Pos 8U |
FPCCR: MONRDY Position
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
| #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) |
FPCCR: Security status of the FP context bit Mask
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
| #define FPU_FPCCR_S_Pos 2U |
FPCCR: Security status of the FP context bit Position
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
| #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) |
FPCCR: SFRDY bit Mask
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
| #define FPU_FPCCR_SFRDY_Pos 7U |
FPCCR: SFRDY Position
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
| #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) |
FPCCR: SPLIMVIOL bit Mask
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
| #define FPU_FPCCR_SPLIMVIOL_Pos 9U |
FPCCR: SPLIMVIOL Position
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
| #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) |
FPCCR: processor mode active bit Mask
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
| #define FPU_FPCCR_THREAD_Pos 3U |
FPCCR: processor mode bit Position
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
| #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) |
FPCCR: TS bit Mask
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
| #define FPU_FPCCR_TS_Pos 26U |
FPCCR: TS Position
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
| #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) |
FPCCR: UFRDY bit Mask
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
| #define FPU_FPCCR_UFRDY_Pos 10U |
FPCCR: UFRDY Position
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
| #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) |
FPCCR: privilege level bit Mask
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
| #define FPU_FPCCR_USER_Pos 1U |
FPCCR: privilege level bit Position
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
| #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) |
FPDSCR: AHP bit Mask
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
| #define FPU_FPDSCR_AHP_Pos 26U |
FPDSCR: AHP bit Position
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
| #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) |
FPDSCR: DN bit Mask
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
| #define FPU_FPDSCR_DN_Pos 25U |
FPDSCR: DN bit Position
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
| #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) |
FPDSCR: FZ bit Mask
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
| #define FPU_FPDSCR_FZ_Pos 24U |
FPDSCR: FZ bit Position
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
| #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) |
FPDSCR: RMode bit Mask
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
| #define FPU_FPDSCR_RMode_Pos 22U |
FPDSCR: RMode bit Position
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
| #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) |
MVFR0: A_SIMD registers bits Mask
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
| #define FPU_MVFR0_A_SIMD_registers_Pos 0U |
MVFR0: A_SIMD registers bits Position
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) |
MVFR0: Divide bits Mask
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
| #define FPU_MVFR0_Divide_Pos 16U |
MVFR0: Divide bits Position
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
| #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) |
MVFR0: Double-precision bits Mask
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
| #define FPU_MVFR0_Double_precision_Pos 8U |
MVFR0: Double-precision bits Position
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
| #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) |
MVFR0: FP exception trapping bits Mask
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
| #define FPU_MVFR0_FP_excep_trapping_Pos 12U |
MVFR0: FP exception trapping bits Position
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
| #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) |
MVFR0: FP rounding modes bits Mask
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
| #define FPU_MVFR0_FP_rounding_modes_Pos 28U |
MVFR0: FP rounding modes bits Position
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
| #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) |
MVFR0: Short vectors bits Mask
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
| #define FPU_MVFR0_Short_vectors_Pos 24U |
MVFR0: Short vectors bits Position
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
| #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) |
MVFR0: Single-precision bits Mask
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
| #define FPU_MVFR0_Single_precision_Pos 4U |
MVFR0: Single-precision bits Position
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
| #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) |
MVFR0: Square root bits Mask
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
| #define FPU_MVFR0_Square_root_Pos 20U |
MVFR0: Square root bits Position
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
| #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) |
MVFR1: D_NaN mode bits Mask
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
| #define FPU_MVFR1_D_NaN_mode_Pos 4U |
MVFR1: D_NaN mode bits Position
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
| #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) |
MVFR1: FP fused MAC bits Mask
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
| #define FPU_MVFR1_FP_fused_MAC_Pos 28U |
MVFR1: FP fused MAC bits Position
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
| #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) |
MVFR1: FP HPFP bits Mask
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
| #define FPU_MVFR1_FP_HPFP_Pos 24U |
MVFR1: FP HPFP bits Position
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
| #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) |
MVFR1: FtZ mode bits Mask
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
| #define FPU_MVFR1_FtZ_mode_Pos 0U |
MVFR1: FtZ mode bits Position
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
IPSR: ISR Mask
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define IPSR_ISR_Pos 0U |
IPSR: ISR Position
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_BASE (0xE0000000UL) |
ITM Base Address
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) |
ITM IMCR: INTEGRATION Mask
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IMCR_INTEGRATION_Pos 0U |
ITM IMCR: INTEGRATION Position
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) |
ITM IRR: ATREADYM Mask
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IRR_ATREADYM_Pos 0U |
ITM IRR: ATREADYM Position
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) |
ITM IWR: ATVALIDM Mask
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_IWR_ATVALIDM_Pos 0U |
ITM IWR: ATVALIDM Position
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) |
ITM LSR: Access Mask
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_Access_Pos 1U |
ITM LSR: Access Position
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) |
ITM LSR: ByteAcc Mask
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_ByteAcc_Pos 2U |
ITM LSR: ByteAcc Position
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) |
ITM LSR: Present Mask
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_LSR_Present_Pos 0U |
ITM LSR: Present Position
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
| #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) |
ITM STIM: DISABLED Mask
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
| #define ITM_STIM_DISABLED_Pos 1U |
ITM STIM: DISABLED Position
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
| #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) |
ITM STIM: FIFOREADY Mask
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
| #define ITM_STIM_FIFOREADY_Pos 0U |
ITM STIM: FIFOREADY Position
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) |
ITM TCR: BUSY Mask
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_BUSY_Pos 23U |
ITM TCR: BUSY Position
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) |
ITM TCR: DWTENA Mask
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_DWTENA_Pos 3U |
ITM TCR: DWTENA Position
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) |
ITM TCR: Global timestamp frequency Mask
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_GTSFREQ_Pos 10U |
ITM TCR: Global timestamp frequency Position
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) |
ITM TCR: ITM Enable bit Mask
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_ITMENA_Pos 0U |
ITM TCR: ITM Enable bit Position
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
| #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) |
ITM TCR: STALLENA Mask
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
| #define ITM_TCR_STALLENA_Pos 5U |
ITM TCR: STALLENA Position
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) |
ITM TCR: SWOENA Mask
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SWOENA_Pos 4U |
ITM TCR: SWOENA Position
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) |
ITM TCR: SYNCENA Mask
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_SYNCENA_Pos 2U |
ITM TCR: SYNCENA Position
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) |
ITM TCR: ATBID Mask
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TRACEBUSID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TraceBusID_Pos 16U |
ITM TCR: ATBID Position
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) |
ITM TCR: TSENA Mask
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSENA_Pos 1U |
ITM TCR: TSENA Position
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
| #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) |
ITM TCR: TSPRESCALE Mask
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
| #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) |
ITM TCR: TSPrescale Mask
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
| #define ITM_TCR_TSPRESCALE_Pos 8U |
ITM TCR: TSPRESCALE Position
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
| #define ITM_TCR_TSPrescale_Pos 8U |
ITM TCR: TSPrescale Position
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) |
ITM TPR: PRIVMASK Mask
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define ITM_TPR_PRIVMASK_Pos 0U |
ITM TPR: PRIVMASK Position
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_BASE (SCS_BASE + 0x0100UL) |
NVIC Base Address
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) |
STIR: INTLINESNUM Mask
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define NVIC_STIR_INTID_Pos 0U |
STIR: INTLINESNUM Position
| #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) |
SCB ABFSR: AHBP Mask
| #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) |
SCB ABFSR: AHBP Mask
| #define SCB_ABFSR_AHBP_Pos 2U |
SCB ABFSR: AHBP Position
| #define SCB_ABFSR_AHBP_Pos 2U |
SCB ABFSR: AHBP Position
| #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) |
SCB ABFSR: AXIM Mask
| #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) |
SCB ABFSR: AXIM Mask
| #define SCB_ABFSR_AXIM_Pos 3U |
SCB ABFSR: AXIM Position
| #define SCB_ABFSR_AXIM_Pos 3U |
SCB ABFSR: AXIM Position
| #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) |
SCB ABFSR: AXIMTYPE Mask
| #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) |
SCB ABFSR: AXIMTYPE Mask
| #define SCB_ABFSR_AXIMTYPE_Pos 8U |
SCB ABFSR: AXIMTYPE Position
| #define SCB_ABFSR_AXIMTYPE_Pos 8U |
SCB ABFSR: AXIMTYPE Position
| #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) |
SCB ABFSR: DTCM Mask
| #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) |
SCB ABFSR: DTCM Mask
| #define SCB_ABFSR_DTCM_Pos 1U |
SCB ABFSR: DTCM Position
| #define SCB_ABFSR_DTCM_Pos 1U |
SCB ABFSR: DTCM Position
| #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) |
SCB ABFSR: EPPB Mask
| #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) |
SCB ABFSR: EPPB Mask
| #define SCB_ABFSR_EPPB_Pos 4U |
SCB ABFSR: EPPB Position
| #define SCB_ABFSR_EPPB_Pos 4U |
SCB ABFSR: EPPB Position
| #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) |
SCB ABFSR: ITCM Mask
| #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) |
SCB ABFSR: ITCM Mask
| #define SCB_ABFSR_ITCM_Pos 0U |
SCB ABFSR: ITCM Position
| #define SCB_ABFSR_ITCM_Pos 0U |
SCB ABFSR: ITCM Position
| #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) |
SCB AHBPCR: EN Mask
| #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) |
SCB AHBPCR: EN Mask
| #define SCB_AHBPCR_EN_Pos 0U |
SCB AHBPCR: EN Position
| #define SCB_AHBPCR_EN_Pos 0U |
SCB AHBPCR: EN Position
| #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) |
SCB AHBPCR: SZ Mask
| #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) |
SCB AHBPCR: SZ Mask
| #define SCB_AHBPCR_SZ_Pos 1U |
SCB AHBPCR: SZ Position
| #define SCB_AHBPCR_SZ_Pos 1U |
SCB AHBPCR: SZ Position
| #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) |
SCB AHBSCR: CTL Mask
| #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) |
SCB AHBSCR: CTL Mask
| #define SCB_AHBSCR_CTL_Pos 0U |
SCB AHBSCR: CTL Position
| #define SCB_AHBSCR_CTL_Pos 0U |
SCB AHBSCR: CTL Position
| #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) |
SCB AHBSCR: INITCOUNT Mask
| #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) |
SCB AHBSCR: INITCOUNT Mask
| #define SCB_AHBSCR_INITCOUNT_Pos 11U |
SCB AHBSCR: INITCOUNT Position
| #define SCB_AHBSCR_INITCOUNT_Pos 11U |
SCB AHBSCR: INITCOUNT Position
| #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) |
SCB AHBSCR: TPRI Mask
| #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) |
SCB AHBSCR: TPRI Mask
| #define SCB_AHBSCR_TPRI_Pos 2U |
SCB AHBSCR: TPRI Position
| #define SCB_AHBSCR_TPRI_Pos 2U |
SCB AHBSCR: TPRI Position
| #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) |
SCB AIRCR: BFHFNMINS Mask
| #define SCB_AIRCR_BFHFNMINS_Pos 13U |
SCB AIRCR: BFHFNMINS Position
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Pos 15U |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Pos 8U |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) |
SCB AIRCR: PRIS Mask
| #define SCB_AIRCR_PRIS_Pos 14U |
SCB AIRCR: PRIS Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Pos 2U |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) |
SCB AIRCR: SYSRESETREQS Mask
| #define SCB_AIRCR_SYSRESETREQS_Pos 3U |
SCB AIRCR: SYSRESETREQS Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Pos 16U |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16U |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) |
SCB AIRCR: VECTRESET Mask
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Pos 0U |
SCB AIRCR: VECTRESET Position
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_BASE (SCS_BASE + 0x0D00UL) |
System Control Block Base Address
| #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) |
SCB CACR: ECCEN Mask
| #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) |
SCB CACR: ECCEN Mask
| #define SCB_CACR_ECCEN_Pos 1U |
SCB CACR: ECCEN Position
| #define SCB_CACR_ECCEN_Pos 1U |
SCB CACR: ECCEN Position
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
| #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) |
SCB CACR: FORCEWT Mask
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
| #define SCB_CACR_FORCEWT_Pos 2U |
SCB CACR: FORCEWT Position
| #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) |
SCB CACR: SIWT Mask
| #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) |
SCB CACR: SIWT Mask
| #define SCB_CACR_SIWT_Pos 0U |
SCB CACR: SIWT Position
| #define SCB_CACR_SIWT_Pos 0U |
SCB CACR: SIWT Position
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Pos 8U |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) |
SCB CCR: BP Mask
SCB CCR: Branch prediction enable bit Mask
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_BP_Pos 18U |
SCB CCR: BP Position
SCB CCR: Branch prediction enable bit Position
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) |
SCB CCR: DC Mask
SCB CCR: Cache enable bit Mask
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DC_Pos 16U |
SCB CCR: DC Position
SCB CCR: Cache enable bit Position
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Pos 4U |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) |
SCB CCR: IC Mask
SCB CCR: Instruction cache enable bit Mask
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_IC_Pos 17U |
SCB CCR: IC Position
SCB CCR: Instruction cache enable bit Position
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Pos 0U |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Pos 9U |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) |
SCB CCR: STKOFHFNMIGN Mask
| #define SCB_CCR_STKOFHFNMIGN_Pos 10U |
SCB CCR: STKOFHFNMIGN Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Pos 3U |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Pos 1U |
SCB CCR: USERSETMPEND Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) |
SCB CCSIDR: Associativity Mask
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U |
SCB CCSIDR: Associativity Position
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) |
SCB CCSIDR: LineSize Mask
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_LINESIZE_Pos 0U |
SCB CCSIDR: LineSize Position
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) |
SCB CCSIDR: NumSets Mask
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_NUMSETS_Pos 13U |
SCB CCSIDR: NumSets Position
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) |
SCB CCSIDR: RA Mask
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_RA_Pos 29U |
SCB CCSIDR: RA Position
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) |
SCB CCSIDR: WA Mask
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WA_Pos 28U |
SCB CCSIDR: WA Position
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) |
SCB CCSIDR: WB Mask
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WB_Pos 30U |
SCB CCSIDR: WB Position
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) |
SCB CCSIDR: WT Mask
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CCSIDR_WT_Pos 31U |
SCB CCSIDR: WT Position
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) |
SCB CFSR (BFSR): BFARVALID Mask
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) |
SCB CFSR (BFSR): BFARVALID Position
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Pos 8U |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) |
SCB CFSR (MMFSR): DACCVIOL Mask
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) |
SCB CFSR (MMFSR): DACCVIOL Position
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) |
SCB CFSR (UFSR): DIVBYZERO Mask
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) |
SCB CFSR (UFSR): DIVBYZERO Position
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) |
SCB CFSR (MMFSR): IACCVIOL Mask
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) |
SCB CFSR (MMFSR): IACCVIOL Position
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) |
SCB CFSR (BFSR): IBUSERR Mask
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) |
SCB CFSR (BFSR): IBUSERR Position
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) |
SCB CFSR (BFSR): IMPRECISERR Mask
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) |
SCB CFSR (BFSR): IMPRECISERR Position
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) |
SCB CFSR (UFSR): INVPC Mask
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) |
SCB CFSR (UFSR): INVPC Position
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) |
SCB CFSR (UFSR): INVSTATE Mask
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) |
SCB CFSR (UFSR): INVSTATE Position
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) |
SCB CFSR (BFSR): LSPERR Mask
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) |
SCB CFSR (BFSR): LSPERR Position
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Pos 0U |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) |
SCB CFSR (MMFSR): MLSPERR Mask
| #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) |
SCB CFSR (MMFSR): MLSPERR Position
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) |
SCB CFSR (MMFSR): MMARVALID Mask
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) |
SCB CFSR (MMFSR): MMARVALID Position
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) |
SCB CFSR (MMFSR): MSTKERR Mask
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) |
SCB CFSR (MMFSR): MSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) |
SCB CFSR (MMFSR): MUNSTKERR Mask
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) |
SCB CFSR (MMFSR): MUNSTKERR Position
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) |
SCB CFSR (UFSR): NOCP Mask
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) |
SCB CFSR (UFSR): NOCP Position
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) |
SCB CFSR (BFSR): PRECISERR Mask
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) |
SCB CFSR (BFSR): PRECISERR Position
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) |
SCB CFSR (BFSR): STKERR Mask
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) |
SCB CFSR (BFSR): STKERR Position
| #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) |
SCB CFSR (UFSR): STKOF Mask
| #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) |
SCB CFSR (UFSR): STKOF Position
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) |
SCB CFSR (UFSR): UNALIGNED Mask
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) |
SCB CFSR (UFSR): UNALIGNED Position
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) |
SCB CFSR (UFSR): UNDEFINSTR Mask
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) |
SCB CFSR (UFSR): UNDEFINSTR Position
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) |
SCB CFSR (BFSR): UNSTKERR Mask
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) |
SCB CFSR (BFSR): UNSTKERR Position
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Pos 16U |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) |
SCB CLIDR: LoC Mask
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOC_Pos 24U |
SCB CLIDR: LoC Position
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) |
SCB CLIDR: LoUU Mask
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CLIDR_LOUU_Pos 27U |
SCB CLIDR: LoUU Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Pos 16U |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Pos 24U |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Pos 4U |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) |
SCB CPUID: REVISION Mask
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Pos 0U |
SCB CPUID: REVISION Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Pos 20U |
SCB CPUID: VARIANT Position
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) |
SCB CSSELR: InD Mask
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_IND_Pos 0U |
SCB CSSELR: InD Position
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) |
SCB CSSELR: Level Mask
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CSSELR_LEVEL_Pos 1U |
SCB CSSELR: Level Position
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) |
SCB CTR: CWG Mask
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_CWG_Pos 24U |
SCB CTR: CWG Position
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) |
SCB CTR: DminLine Mask
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_DMINLINE_Pos 16U |
SCB CTR: DminLine Position
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) |
SCB CTR: ERG Mask
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_ERG_Pos 20U |
SCB CTR: ERG Position
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) |
SCB CTR: Format Mask
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_FORMAT_Pos 29U |
SCB CTR: Format Position
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) |
SCB CTR: ImInLine Mask
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_CTR_IMINLINE_Pos 0U |
SCB CTR: ImInLine Position
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) |
SCB DCCISW: Set Mask
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_SET_Pos 5U |
SCB DCCISW: Set Position
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) |
SCB DCCISW: Way Mask
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCISW_WAY_Pos 30U |
SCB DCCISW: Way Position
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) |
SCB DCCSW: Set Mask
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_SET_Pos 5U |
SCB DCCSW: Set Position
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) |
SCB DCCSW: Way Mask
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCCSW_WAY_Pos 30U |
SCB DCCSW: Way Position
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) |
SCB DCISW: Set Mask
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_SET_Pos 5U |
SCB DCISW: Set Position
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) |
SCB DCISW: Way Mask
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DCISW_WAY_Pos 30U |
SCB DCISW: Way Position
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Pos 1U |
SCB DFSR: BKPT Position
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Pos 2U |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Pos 4U |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) |
SCB DFSR: HALTED Mask
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Pos 0U |
SCB DFSR: HALTED Position
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Pos 3U |
SCB DFSR: VCATCH Position
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
| #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) |
SCB DTCMCR: EN Mask
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
| #define SCB_DTCMCR_EN_Pos 0U |
SCB DTCMCR: EN Position
| #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) |
SCB DTCMCR: RETEN Mask
| #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) |
SCB DTCMCR: RETEN Mask
| #define SCB_DTCMCR_RETEN_Pos 2U |
SCB DTCMCR: RETEN Position
| #define SCB_DTCMCR_RETEN_Pos 2U |
SCB DTCMCR: RETEN Position
| #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) |
SCB DTCMCR: RMW Mask
| #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) |
SCB DTCMCR: RMW Mask
| #define SCB_DTCMCR_RMW_Pos 1U |
SCB DTCMCR: RMW Position
| #define SCB_DTCMCR_RMW_Pos 1U |
SCB DTCMCR: RMW Position
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
| #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) |
SCB DTCMCR: SZ Mask
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
| #define SCB_DTCMCR_SZ_Pos 3U |
SCB DTCMCR: SZ Position
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Pos 31U |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Pos 30U |
SCB HFSR: FORCED Position
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Pos 1U |
SCB HFSR: VECTTBL Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Pos 22U |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Pos 23U |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
SCB ICSR: NMIPENDSET Mask, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk |
SCB ICSR: NMIPENDSET Mask, backward compatibility
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
SCB ICSR: NMIPENDSET Position, backward compatibility
| #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos |
SCB ICSR: NMIPENDSET Position, backward compatibility
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Pos 31U |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) |
SCB ICSR: PENDNMICLR Mask
| #define SCB_ICSR_PENDNMICLR_Pos 30U |
SCB ICSR: PENDNMICLR Position
| #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) |
SCB ICSR: PENDNMISET Mask
| #define SCB_ICSR_PENDNMISET_Pos 31U |
SCB ICSR: PENDNMISET Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Pos 25U |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Pos 26U |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Pos 27U |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Pos 28U |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Pos 11U |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) |
SCB ICSR: STTNS Mask (Security Extension)
| #define SCB_ICSR_STTNS_Pos 24U |
SCB ICSR: STTNS Position (Security Extension)
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Pos 0U |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Pos 12U |
SCB ICSR: VECTPENDING Position
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
| #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) |
SCB ITCMCR: EN Mask
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
| #define SCB_ITCMCR_EN_Pos 0U |
SCB ITCMCR: EN Position
| #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) |
SCB ITCMCR: RETEN Mask
| #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) |
SCB ITCMCR: RETEN Mask
| #define SCB_ITCMCR_RETEN_Pos 2U |
SCB ITCMCR: RETEN Position
| #define SCB_ITCMCR_RETEN_Pos 2U |
SCB ITCMCR: RETEN Position
| #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) |
SCB ITCMCR: RMW Mask
| #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) |
SCB ITCMCR: RMW Mask
| #define SCB_ITCMCR_RMW_Pos 1U |
SCB ITCMCR: RMW Position
| #define SCB_ITCMCR_RMW_Pos 1U |
SCB ITCMCR: RMW Position
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
| #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) |
SCB ITCMCR: SZ Mask
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
| #define SCB_ITCMCR_SZ_Pos 3U |
SCB ITCMCR: SZ Position
| #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) |
SCB NSACR: CP10 Mask
| #define SCB_NSACR_CP10_Pos 10U |
SCB NSACR: CP10 Position
| #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) |
SCB NSACR: CP11 Mask
| #define SCB_NSACR_CP11_Pos 11U |
SCB NSACR: CP11 Position
| #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) |
SCB NSACR: CPn Mask
| #define SCB_NSACR_CPn_Pos 0U |
SCB NSACR: CPn Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Pos 4U |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Pos 2U |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) |
SCB SCR: SLEEPDEEPS Mask
| #define SCB_SCR_SLEEPDEEPS_Pos 3U |
SCB SCR: SLEEPDEEPS Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Pos 1U |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Pos 1U |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Pos 17U |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) |
SCB SHCSR: HARDFAULTACT Mask
| #define SCB_SHCSR_HARDFAULTACT_Pos 2U |
SCB SHCSR: HARDFAULTACT Position
| #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) |
SCB SHCSR: HARDFAULTPENDED Mask
| #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U |
SCB SHCSR: HARDFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Pos 0U |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Pos 16U |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Pos 8U |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) |
SCB SHCSR: NMIACT Mask
| #define SCB_SHCSR_NMIACT_Pos 5U |
SCB SHCSR: NMIACT Position
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Pos 10U |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) |
SCB SHCSR: SECUREFAULTACT Mask
| #define SCB_SHCSR_SECUREFAULTACT_Pos 4U |
SCB SHCSR: SECUREFAULTACT Position
| #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) |
SCB SHCSR: SECUREFAULTENA Mask
| #define SCB_SHCSR_SECUREFAULTENA_Pos 19U |
SCB SHCSR: SECUREFAULTENA Position
| #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) |
SCB SHCSR: SECUREFAULTPENDED Mask
| #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U |
SCB SHCSR: SECUREFAULTPENDED Position
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Pos 7U |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Pos 15U |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Pos 11U |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Pos 3U |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Pos 18U |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12U |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) |
SCB STIR: INTID Mask
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_STIR_INTID_Pos 0U |
SCB STIR: INTID Position
| #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) |
SCB VTOR: TBLBASE Mask
| #define SCB_VTOR_TBLBASE_Pos 29U |
SCB VTOR: TBLBASE Position
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Pos 7U |
SCB VTOR: TBLOFF Position
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) |
System control Register not in SCB
| #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
| #define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SCS_BASE (0xE000E000UL) |
System Control Space Base Address
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick ((SysTick_Type *) SysTick_BASE ) |
SysTick configuration struct
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_BASE (SCS_BASE + 0x0010UL) |
SysTick Base Address
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) |
SysTick CALIB: NOREF Mask
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_NOREF_Pos 31U |
SysTick CALIB: NOREF Position
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) |
SysTick CALIB: SKEW Mask
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_SKEW_Pos 30U |
SysTick CALIB: SKEW Position
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) |
SysTick CALIB: TENMS Mask
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CALIB_TENMS_Pos 0U |
SysTick CALIB: TENMS Position
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) |
SysTick CTRL: CLKSOURCE Mask
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_CLKSOURCE_Pos 2U |
SysTick CTRL: CLKSOURCE Position
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) |
SysTick CTRL: COUNTFLAG Mask
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_COUNTFLAG_Pos 16U |
SysTick CTRL: COUNTFLAG Position
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) |
SysTick CTRL: ENABLE Mask
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_ENABLE_Pos 0U |
SysTick CTRL: ENABLE Position
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) |
SysTick CTRL: TICKINT Mask
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_CTRL_TICKINT_Pos 1U |
SysTick CTRL: TICKINT Position
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) |
SysTick LOAD: RELOAD Mask
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_LOAD_RELOAD_Pos 0U |
SysTick LOAD: RELOAD Position
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) |
SysTick VAL: CURRENT Mask
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define SysTick_VAL_CURRENT_Pos 0U |
SysTick VAL: CURRENT Position
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_BASE (0xE0040000UL) |
TPI Base Address
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
| #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
| #define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
| #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFO depth Mask
TPI DEVID: FIFOSZ Mask
| #define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
TPI DEVID: FIFOSZ Position
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
| #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
| #define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
| #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
| #define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
| #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
| #define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
| #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
| #define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
| #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
| #define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
| #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
| #define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
| #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
| #define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
| #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
| #define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
| #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
| #define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
| #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
| #define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
| #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
| #define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
| #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
| #define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
| #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
| #define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
| #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
| #define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
| #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
| #define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
| #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
| #define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
| #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
| #define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
| #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
| #define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
| #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
| #define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
| #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
| #define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
xPSR: C Mask
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_C_Pos 29U |
xPSR: C Position
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
| #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) |
xPSR: GE Mask
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
| #define xPSR_GE_Pos 16U |
xPSR: GE Position
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
xPSR: ICI/IT part 1 Mask
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
| #define xPSR_ICI_IT_1_Pos 10U |
xPSR: ICI/IT part 1 Position
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
xPSR: ICI/IT part 2 Mask
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
| #define xPSR_ICI_IT_2_Pos 25U |
xPSR: ICI/IT part 2 Position
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
xPSR: ISR Mask
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_ISR_Pos 0U |
xPSR: ISR Position
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
| #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) |
xPSR: IT Mask
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
| #define xPSR_IT_Pos 25U |
xPSR: IT Position
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
xPSR: N Mask
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_N_Pos 31U |
xPSR: N Position
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
xPSR: Q Mask
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_Q_Pos 27U |
xPSR: Q Position
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
xPSR: T Mask
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_T_Pos 24U |
xPSR: T Position
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
xPSR: V Mask
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_V_Pos 28U |
xPSR: V Position
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
xPSR: Z Mask
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position
| #define xPSR_Z_Pos 30U |
xPSR: Z Position